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    Bao Liu

    Electrical and Computer Engineering Department
    The University of Texas at San Antonio
    San Antonio, TX 78249-0669
    Phone: (210) 458-5568
    Fax: (210) 458-5947
    Email: bliu@utsa.edu
    Office: BSE 1.514


  • 8/3/15: Dr. Liu gave an invited tutorial on "Hardware Security in IoT Era: Challenges and Opportunities" at Asia Symposium on Quality Electricl Design.
  • 7/2/15: Dr. Liu was invited to moderate an ICCAD session on hardware security.
  • 6/8/15: Dr. Liu joined ICCD TPC.
  • 5/11/15: Dr. Liu was invited to serve as Chair of the Hardware and System Security track in International Symposium on Quality Electricl Design 2016.
  • 4/28/15: Congratulations to Yao Chen and Xutao Wang for successfully defending their master theses.
  • 3/9/15: Our paper on signal probability-based telescopic VLSI design has been accepted to appear in ACM Journal of Emerging Technologies in Computing Systems (more).
  • 3/3/15: Dr. Liu moderated an industry panel on Hardware and System Security at International Symposium on Quality Electricl Design (more).

Dr. Bao Liu received his B.S. and M.S. degrees in Electrical Engineering at Fudan University in 1993 and 1996, and his Ph.D. degree in Computer Science at the University of California San Diego in 2003, respectively. He worked with a couple of industry companies (China IC Design Center, Conexant Systems, Incentia Design Systems, Cadence Design Systems, BlazeDFM, and Tabula), and held a post-doctoral research associate position at the University of California San Diego before joining the ECE department at UTSA. Dr. Liu's research areas include hardware security, nanoscale computing architecture, adaptive and resilient VLSI design, VLSI statistical timing and signal integrity analysis, delay test, and physical design. He has published 18 journal articles, 48 conference papers and 3 PCT/US patents. He has received a Best Paper Award at ICCD in 2005, a Best Research Award in UCSD Research Review in 2002, a China ICCAD Best Member Award in 1996, and a China Mathematics Olympiad Honor in 1988. He has served/been serving as chair/co-chair, TPC member, panel moderator, panelist and reviewer for a number of technical conferences and scientific journals, including chair of the "Hardware and System Security" track at International Symposium on Quality Electronic Design (ISQED) 2015, chair of an invited session "Emerging Nano-Circuits and Systems" at International Midwest Symposium on Circuits and Systems (MWSCAS) 2010, co-chair of the "Emerging Design and Technology" session at International Symposium on Quality Electronic Design (ISQED) 2006 - 2014, moderator for industry panel on "Hardware and System Security" at International Symposium on Quality Electronic Design (ISQED) 2015, and panelist on "CAD for Nanoelectronics" at International Symposium on Nanoscale Architectures (NANOARCH) 2010.

Research Highlights:

  • VLSI Obfuscation based on trusted dies in 3D IC integration or embedded reconfigurable logic modules in ASIC (pdf), Tamper-Evident Architecture (TEA) for dynamic computation integrity verification and detection of malicious programs in hardware (pdf)
  • Variable-Latency VLSI Design of 20-40% average performance improvement at virtually no cost in area and energy for various programs on a SPARC V8 integer unit (pdf), timing and soft-error Resilient and Adaptive maximum Performance (RAP) Logic based on delay-insensitive code (pdf)
  • Carbon Nanotube Crossbar-Based Nano-Architecture (pdf), Voltage-Controlled Nano-Addressing (pdf)
  • Linear and Semidefinite Programs for Optimal Power/Ground Supply Network Decoupling Capacitor Insertion (pdf)
  • Dynamic Statistical Timing Analysis (pdf) and Delay Test (pdf)