Hardware-assisted Security
Cyber security is getting more attention nowadays because our daily life is getting more and more dependent on digital infrastructure. We believe hardware-assisted security is one of the promising areas in the security field because the hardware can serve as a root of trust for security solutions. We are developing a powerful hardware platform that can be used to implement various types of software security solutions so that the software techniques can be protected by hardware mechanisms. In other words, the software protects the host system, and the hardware protects the software from being compromised. Potentially, it could trigger a major paradigm shift in the host-side security.
Networks on Chip
The ever-increasing number of on-chip processing cores necessitates a scalable on-chip communication backbone. On the other hand, the power wall forces the communication architecture to be extremely power-efficient. To achieve these two opposing goals, we proposed a ring-based on-chip router that offers better scalability and incurs less overhead than state-of-the-art low-cost routers.
The flit size is one of key parameters that have significant impact on the performance and cost of on-chip routers. Since there has been no prior discussion on the optimal flit size in networks-on-chip, we made the first attempt to address it considering various aspects of the system. In addition, we proposed a novel router architecture that fully utilizes the physical channel width.
We observed that there is non-negligible amount of single-flit packets in the network. They do not benefit from a worm-hole routing algorithm which is the most well-known flow control algorithm. To expedite the single-flit packets, we proposed a novel on-chip router architecture that logically segregates single-flit packets by a single entity of a router.
Solid State Drives
Garbage collection (GC) is a mechanism that reclaims stale pages to make free space. However, while GC is running, incoming requests cannot be serviced. Since GC takes much longer than read and write operations, it has significant adverse impact on overall system performance. To mitigate the impact of GC, we proposed preemptable GC implementation that allows incoming requests to delay on-going GC and substantially improved the system performance.
Offering high performance as well as high reliability, redundant array of independent disks (RAIDs) are usually employed in storage systems. RAIDs can consist of SSDs. Since it was empirically observed that uncoordinated GC in individual SSDs degrades the overall performance, we augmented coordination mechanisms to the RAID controller and SSDs and enhanced the performance while reducing cost.
A write-buffer can be employed to reduce the access time to SSDs. Instead of flushing pending requests immediately from the write-buffer to the memory, aligning requests across SSDs in the array improves the performance substantially at a minimal cost. In this project, we are investigating the feasibility of several aligning techniques.