Areas of Teaching Interest
VLSI Design, Topics in VLSI Design, Computer Architecture, Topics in Computer Architecture
Areas of Research Interest
Energy Efficient Computing, Ultra-Low Energy Computing for Implantable Cardiac Devices, Efficient Hardware for Machine Learning and Artificial Intelligence, Integrated Circuit IP Security and Trust, Hardware Security, Low Power VLSI Circuits and Systems, Power-Aware and Secure Systems, Power Aware Cloud Computing, Computer Architecture and Performance Evaluation.
Ph.D, Pennsylvania State University
- S. Mostafa and E. John, “Resource Shared Galois Field Computation for Energy Efficient AES/CRC in IoT Applications”, accepted for publications, IEEE Transactions on Sustainable Computing.
- A. Owahid, and E. John “Instruction Profiling Based Fetch Throttling for Wasted Dynamic Power Reduction”, 31st International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2019, October 15-18 – Campo Grande, MS, Brazil.
- S. Mostafa, E. John and M. Panday, “Design and Implementation of an Ultra-Low Energy FFT ASIC for Processing ECG in Cardiac Pacemakers”, IEEE Transactions on VLSI Systems, Vol. 27. No. 4, pp. 983- 987, 2019.
- L. John, S. Verma, Q. Wu, B. Hanindhito, R. Radhakrishnan, G, Jha and E. John, “Demystifying Hardware Infrastructure Choices for Deep Learning using MLPref”, NVIDIA GPU Technology Conference (GTC-2019), San Jose, CA, March 2019.
- S. Verma, Q. Wu, B. Hanindhito, G. Jha, E. John, R. Radhakrishnan, and L. K. John, “Metrics for Machine Learning Workload Benchmarking”, International Workshop on Performance Analysis of Machine Learning Systems (FastPath) in conjunction with ISPASS 2019. March 2019.
- J. Whitehouse, Q. Wu, S. Song, E. John, A. Gerstlauer, and L. K. John, “A Study of Core Utilization and Residency in Heterogeneous Smartphone Architectures”, ACM International Conference on Performance Engineering (ICPE). April 2019.
- E. Tolliver and E. John, “Power Reduction in CNNs by Modifying Floating Point Number Format for Machine Learning” 4th Annual Samsung Austin Research Center Technology Forum, Austin, TX, Oct 16, 2018.
- G. Jha and E. John, “Performance Analysis of Single-Precision Floating-Point MAC for Deep Learning”, 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2018), Windsor, ON, Canada, August 5th-8th, 2018.
- Hao Yan, Lei Jiang, Lide Duan, Wei-Ming Lin and E. John, “FlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance”, in ACM Transactions on Embedded Computing Systems (TECS), Volume 16 Issue 5s, October 2017.
- J. Portillo, E. John and S. Narasimhan, “Building Trust in 3PIP using Asset-based Security Property Verification” IEEE VLSI Test Symposium 2016, Las Vegas, NV, April 25-27, 2016.
- S. Mostafa and E. John, “Reducing Power and Cycle Requirement for Fast Fourier Transform of Electrocardiogram Signals Through Low Level Arithmetic Optimizations for Cardiac Implantable Devices”, Journal of Low Power Electronics, Volume 12, Number 1, March 2016, pp. 21-29(9).
- S. Mostafa and E. John “Performance and Energy Evaluation of ARM Cortex Variants for Smart Cardiac Pacemaker Application”, The 2nd International Conference on Biomedical Engineering and Sciences (BIOENG’16), Las Vegas, NV, July 25 – 28, 2016.
- S. Erathne, P.S. Nair and E. John, “A Thermal-Aware Scheduling Algorithm for Core Migration in Multicore Processors”, Journal of Low Power Electronics, pp. 103 – 111, June 2015.
- S. Mostafa and E. John “Evaluation of Embedded ISAs for Smart Cardiac Pacemaker Workloads”, in the Proceedings of the 2015 International Conference on Biomedical Engineering and Sciences (BIOENG’15), Las Vegas, NV, July 27-30, 2015.
- N. Ferdous. B. Lee and E. John, “Performance Enhancement in Shared-Memory Multiprocessors Using Dynamically Classified Sharing Information” 33rd IEEE – International Performance Computing and Communications Conference (IPCCC- 2014), Austin, TX, Dec 5 – 7, 2014.
- P. S. Nair, S. Erathne and E. John, “Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance”, Journal of Low Power Electronics. Volume 8, Number 1, pp. 1-8, April 2012.
- Binu. P. John, A. Agrawal, B. Steigerwald and E. John, “Impact of Operating System Behavior on Battery Life”. Journal of Low Power Electronics. Volume 6, Number 1, pp. 10-17, April 2010
- D. Kudithipudi, S. Petko and E. John “Caches for Multimedia Workloads: Power and Energy Trade-offs”, IEEE Transactions on Multimedia, Vol. 10, No. 6, pp. 1013 – 1021 October, 2008.
- B. K. Lee, L. K. John and E. John, “Architectural Enhancements for Network Congestion Control Applications” IEEE Transactions on VLSI Systems, Vol. 14, No. 6, pp. 609-615, June, 2006